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Freescale Semiconductor Data Sheet: Advance Information
Document Number: MCF51AC256 Rev.1 , 06/2008
MCF51AC256
80 LQFP 14 mm x 14 mm 64 LQFP 10 mm x 10 mm
MCF51AC256 ColdFire Microcontroller
The MCF51AC256 is a member of the ColdFire(R) family of 32-bit variable-length reduced instruction set (RISC) microcontroller. This document provides an overview of the MCF51AC256 series, focusing on its highly integrated and diverse feature set. The MCF51AC256 series is based on the V1 ColdFire core and operates at processor core speeds up to 50.33 MHz. As part of Freescale's Controller Continuum(R), it is an ideal upgrade for designs based on the MC9S08AC128 series of 8-bit microcontrollers. The MCF51AC256 features the following functional units: * V1 ColdFire core with background debug module * Up to 256 KBytes of flash memory * Up to 32 Kbytes of static RAM (SRAM) * Up to two analog comparators (ACMP) * Analog-to-digital converter (ADC) with up to 24 channels * Controller-area network (CAN) * Cyclic redundancy check (CRC) * Inter-integrated circuit (IIC) * Keyboard interrupt (KBI) * Multipurpose clock generator (MCG) * Rapid general-purpose input/output (RGPIO) * Two serial communications interfaces (SCI) * Up to two serial parallel interfaces (SPI) * Two flexible timer modules (FTM) * Timer pulse-width modulator (TPM)
64 QFP 14 mm x 14 mm
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2008. All rights reserved. Preliminary--Subject to Change Without Notice
Table of Contents
1 MCF51AC256 Family Configurations . . . . . . . . . . . . . . . . . . . .3 1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.4 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.5 Pinouts and Packaging . . . . . . . . . . . . . . . . . . . . . . . . .10 Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .14 2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .14 2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .14 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15 2.4 Electrostatic Discharge (ESD) Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . .16 2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .22 2.7 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .23 2.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.9 External Oscillator (XOSC) Characteristics . . . . . . . . .26 2.10 MCG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.11.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.11.2 Timer (TPM/FTM) Module Timing . . . . . . . . . . .30 2.11.3 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.12 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.14 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.14.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .35 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .36 3.1 80-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .36 3.2 64-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .39 3.3 64-pin QFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . .42 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Figure 6. Typical IOH vs. VDD-VOH at VDD = 5V (Low Drive, PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . Figure 7. Typical IOH vs. VDD-VOH at VDD = 5 V (High Drive, PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . Figure 8. ADC Input Impedance Equivalency Diagram . . . . . . . Figure 9. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . . Figure 13.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . Figure 14.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . Figure 15.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . Figure 16.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 21 21 24 29 30 30 31 33 33 34 34
2
List of Tables
Table 1. MCF51AC256 Series Device Comparison . . . . . . . . . . 3 Table 2. MCF51AC256 Series Functional Units . . . . . . . . . . . . . 5 Table 3. Orderable Part Number Summary. . . . . . . . . . . . . . . . . 9 Table 4. Pin Availability by Package Pin-Count . . . . . . . . . . . . . 11 Table 5. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 14 Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 15 Table 7. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 15 Table 8. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 16 Table 10.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. ESD and Latch-Up Protection Characteristics. . . . . . . 17 Table 11. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 22 Table 12.Analog Comparator Electrical Specifications. . . . . . . . 23 Table 13.5 Volt 12-bit ADC Operating Conditions . . . . . . . . . . . 23 Table 14.5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) . . . . . . . . . . . . 24 Table 15.Oscillator Electrical Specifications (Temperature Range = -40 to 105xC Ambient) . . . . . 26 Table 16.MCG Frequency Specifications (Temperature Range = -40 to 125xC Ambient) . . . . . 27 Table 17.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 18.TPM/FTM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 19.MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . 31 Table 20.SPI Electrical Characteristic . . . . . . . . . . . . . . . . . . . . 32 Table 21.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 22.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3
4
List of Figures
Figure 1. MCF51AC256 Block Diagram . . . . . . . . . . . . . . . . . . . . 4 Figure 2. 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3. 64-Pin QFP and LQFP . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. Typical IOH vs. VDD-VOH at VDD = 3V (Low Drive, PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . 20 Figure 5. Typical IOH vs. VDD-VOH at VDD = 3V (High Drive, PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . 20
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor
MCF51AC256 Family Configurations
1
1.1
MCF51AC256 Family Configurations
Device Comparison
Table 1. MCF51AC256 Series Device Comparison
MCF51AC256A MCF51AC256B MCF51AC128A Feature 80-pin 64-pin 80-pin 64-pin 80-pin 64-pin 80-pin 64-pin MCF51AC128C
The MCF51AC256 series is summarized in Table 1.
Flash memory size (Kbytes) RAM size (Kbytes) V1 ColdFire core with BDM (background debug module) ACMP1 (analog comparator) ACMP2 (analog comparator) ADC (analog-to-digital converter) channels (12-bit) CAN (controller area network) COP (computer operating properly) CRC (cyclic redundancy check) RTI DBG (debug) IIC1 (inter-integrated circuit) IRQ (interrupt request input) INTC (interrupt controller) KBI (keyboard interrupts) LVD (low-voltage detector) MCG (multipurpose clock generator) OSC (crystal oscillator) Port I/O2 69 54 Yes
256 32 Yes Yes Yes 24 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 69 54 16 Yes Yes Yes No Yes No 6 6 2 6 2 2 Yes No Yes No Yes No 6 2 Yes No 69 54 Yes
128 32 or 161
No
69
54
RGPIO (rapid general-purpose I/O) SCI1, SCI2 (serial communications interfaces) SPI1 (serial peripheral interface) SPI2 (serial peripheral interface) FTM1 (flexible timer module) channels FTM2 channels TPM3 (timer pulse-width modulator) channels VBUS (debug visibility bus)
Yes
No
6
2
Yes
No
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3
MCF51AC256 Family Configurations
1 2
The members of MCF51AC128 with CAN support have 32 K-byte RAM. The other members have 16 K-byte RAM. Up to 16 pins on Ports E and F are shared with the ColdFire Rapid GPIO module.
1.2
VREFH VREFL VDDAD VSSAD
Block Diagram
PTA7/AD1P17 PTA6/AD1P16 PTA5/ACMP2+ PTA4/ACMP2- PTA3/ACMP2O PTA2 PTA1/RXCAN PTA0/TXCAN PTB7/AD1P7 PTB6/AD1P6 PTB5/AD1P5 PTB4/AD1P4 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 PTC6/FTM2FLT PTC5/RxD2 PTC4/SS2 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD7/KBI1P7/AD1P15 PTD6/FTM1CLK/AD1P14 PTD5/AD1P13 PTD4/FTM2CLK/AD1P12 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10/ACMP1O PTD1/AD1P9/ACMP1- PTD0/AD1P8/ACMP1+ PTE7/RGPIO7/SPSCK1 PTE6/RGPIO6/MOSI1 PTE5/RGPIO5/MISO1 PTE4/RGPIO4/SS1 PTE3/RGPIO3/FTM1CH1 PTE2/RGPIO2/FTM1CH0 PTE1/RGPIO1/RxD1 PTE0/RGPIO0/TxD1 PTF7/RGPIO15 PTF6/FTM1FLT/RGPIO14 PTF5/RGPIO13/FTM2CH1 PTF4/RGPIO12/FTM2CH0 PTF3/RGPIO11/FTM1CH5 PTF2/RGPIO10/FTM1CH4 PTF1/RGPIO9/FTM1CH3 PTF0/RGPIO8/FTM1CH2 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4/AD1P19 PTG3/KBI1P3/AD1P18 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 PTH6/MISO2 PTH5/MOSI2 PTH4/SPSCK2 PTH3/FTM2CH5/BKPT/AD1P23 PTH2/FTM2CH4/PSTCLK1/AD1P22 PTH1/FTM2CH3/PSTCLK0/AD1P21 PTH0/FTM2CH2/AD1P20 PTJ7/DDATA3 PTJ6/DDATA2 PTJ5/DDATA1 PTJ4/DDATA0 PTJ3/PST3 PTJ2/PST2 PTJ1/PST1 PTJ0/PST0
Figure 1 shows the connections between the MCF51AC256 series pins and modules.
VREFH VREFL VDDAD VSSAD Port J: DDATA3DDATA0 PST3VBUS PST0 Port H: PSTCLK BKPT Port B: ADP7ADP0 Port D: ADP15ADP8 Port A: ADP17ADP16 Port G: ADP19ADP18 Port H: ADP23ADP20 Port F: FTM1CH5 FTM1CH4 FTM1CH3 FTM1CH2 Port E: FTM1CH1 FTM1CH0 Port H: FTM2CH5 FTM2CH4 FTM2CH3 FTM2CH2 Port F: FTM2CH1 FTM2CH0 Port B: TPM3CH1 TPM3CH0 Port D: ACMP1O ACMP1 ACMP1- ACMP1+ Port A: ACMP2O ACMP2+ Port C: SDA1 SCL1 Port G: KBIP4 KBIP3 KBIP2 KBIP1 KBIP0 Port D: KBIP7 KBIP6 KBIP5 Port B Port J Port H Port G Port F Port E Port D Port C
DBG
ADC
ACMP2 ACMP2-
BKGD/MS
BDM
IIC1
ColdFire V1 core
RESET
TPMCLK
FTM1 SIM
TPMCLK
KBI
IRQ/ TPMCLK
COP
LVD
IRQ FTM2
MCG
OSC
Port G: EXTAL XTAL Port A: RXCAN TXCAN
FLASH
MCF51AC256 = 256 KB MCF51AC128 = 128 KB TPMCLK
CAN TPM3
RAM
MCF51AC256 = 32 KB MCF51AC128 = 16 KB
Port F: RGPIO15 RGPIO14 RGPIO13 RGPIO12 RGPIO11 RGPIO10 RGPIO9 RGPIO8
RGPIO
CRC
SCI1
Port E: RGPIO7 RGPIO6 RGPIO5 RGPIO4 RGPIO3 RGPIO2 RGPIO1 RGPIO0
Port E: RXD1 TXD1 Port C: RXD2 TXD2 Port E: SS1 SPSCK1 MOSI1 MISO1
Port H: SS2
RTC SCI2
SPI1
VDD VSS VSS
VREG
SPI2 SPSCK2
MOSI2 MISO2
Figure 1. MCF51AC256 Block Diagram
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 4 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Port A
MCF51AC256 Family Configurations
1.3
Features
Table 2 describes the functional units of the MCF51AC256 series. Table 2. MCF51AC256 Series Functional Units
Functional Unit CF1CORE (V1 ColdFire core) BDM (background debug module) DBG (debug) VBUS (debug visibility bus) SIM (system integration module) FLASH (flash memory) RAM (random-access memory) RGPIO (rapid general-purpose input/output) VREG (voltage regulator) COP (computer operating properly) LVD (low-voltage detect) CF1_INTC (interrupt controller) ADC (analog-to-digital converter) FTM1, FTM2 (flexible timer/pulse-width modulators) TPM3 (timer/pulse-width modulator) CRC (cyclic redundancy check) ACMP1, ACMP2 (analog comparators) IIC1 (inter-integrated circuit) KBI (keyboard interrupt) MCG (multipurpose clock generator) Function Executes programs and interrupt handlers Provides single pin debugging interface (part of the V1 ColdFire core) Provides debugging and emulation capabilities (part of the V1 ColdFire core) Allows for real-time program traces (part of the V1 ColdFire core) Controls resets and chip level interfaces between modules Provides storage for program code, constants and variables Provides storage for program variables Allows for I/O port access at CPU clock speeds Controls power management across the device Monitors a countdown timer and generates a reset if the timer is not regularly reset by the software Monitors internal and external supply voltage levels, and generates a reset or interrupt when the voltages are too low Controls and prioritizes all device interrupts Measures analog voltages at up to 12 bits of resolution Provide a variety of timing-based features Provides a variety of timing-based features Accelerates computation of CRC values for ranges of memory Compare two analog inputs Supports standard IIC communications protocol Provides pin interrupt capabilities Provides clocking options for the device, including a phase-locked loop (PLL) and frequency-locked loop (FLL) for multiplying slower reference clock sources Allows a crystal or ceramic resonator to be used as the system clock source or reference clock for the PLL or FLL Supports standard CAN communications protocol Serial communications UARTs capable of supporting RS-232 and LIN protocols Provide 8-bit 4-pin synchronous serial interface Provide 16-bit 4-pin synchronous serial interface
OSC (crystal oscillator) CAN (controller area network) SCI1, SCI2 (serial communications interfaces) SPI1 (8-bit serial peripheral interfaces) SPI2 (16-bit serial peripheral interfaces)
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5
MCF51AC256 Family Configurations
1.3.1
*
Feature List
32-bit Version 1 ColdFire(R) central processor unit (CPU) -- Up to 50.33 MHz at 2.7 V - 5.5 V -- Provide 0.94 Dhrystone 2.1 DMIPS per MHz performance when running from internal RAM (0.76 DMIPS per MHz when running from flash) -- Implements instruction set revision C (ISA_C) On-chip memory -- Up to 256 KBytes flash memory read/program/erase over full operating voltage and temperature -- Up to 32 KBytes static random access memory (SRAM) -- Security circuitry to prevent unauthorized access to SRAM and flash contents Power-Saving Modes -- Three low-power stop plus wait modes -- Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode System protection features -- Watchdog computer operating properly (COP) reset -- Low-voltage detection with reset or interrupt -- Illegal opcode and illegal address detection with programmable reset or exception response -- Flash block protection Debug support -- Single-wire background debug interface -- Real-time debug support, with 6 hardware breakpoints (4 PC, 1 address pair and 1 data) that can be configured into a 1- or 2-level trigger -- On-chip trace buffer provides programmable start/stop recording conditions plus support for continuous or PC-profiling modes -- Support for real-time program (and optional partial data) trace using the debug visibility bus V1 ColdFire interrupt controller (CF1_INTC) -- Support of 40 peripheral I/O interrupt requests plus seven software (one per level) interrupt requests -- Fixed association between interrupt request source and level plus priority, up to two requests can be remapped to the highest maskable level + priority -- Unique vector number for each interrupt source -- Support for service routine interrupt acknowledge (software IACK) read cycles for improved system performance Multipurpose clock generator (MCG) -- Oscillator (XOSC); loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz -- FLL/PLL controlled by internal or external reference -- Trimmable internal reference allows 0.2% resolution and 2% deviation Analog-to-digital converter (ADC) -- 24 analog inputs with 12 bits resolution -- Output formatted in 12-, 10- or 8-bit right-justified format -- Single or continuous conversion (automatic return to idle after single conversion) -- Operation in low-power modes for lower noise operation -- Asynchronous clock source for lower noise operation -- Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value -- On-chip temperature sensor
*
*
*
*
*
*
*
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor
MCF51AC256 Family Configurations
*
*
*
*
*
*
Flexible timer/pulse-width modulators (FTM) -- 16-bit Free-running counter or a counter with initial and final value. The counting can be up and unsigned, up and signed, or up-down and unsigned -- Up to 6 channels, and each channel can be configured for input capture, output compare or edge-aligned PWM mode, all channels can be configured for center-aligned PWM mode - Channels can operate as pairs with equal outputs, pairs with complimentary outputs or independent channels (with independent outputs) - Each pair of channels can be combined to generate a PWM signal (with independent control of both edges of PWM signal) - Deadtime insertion is available for each complementary pair -- The load of the FTM registers which have write buffer can be synchronized; write protection for critical registers -- Generation of the triggers to ADC (hardware trigger) -- A fault input for global fault control -- Backwards compatible with TPM Timer/pulse width modulator (TPM) -- 16-bit free-running or modulo up/down count operation -- Two channels, each channel may be input capture, output compare, or edge-aligned PWM -- One interrupt per channel plus terminal count interrupt Cyclic redundancy check (CRC) generator -- High speed hardware CRC generator circuit using 16-bit shift register -- CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial -- Error detection for all single, double, odd, and most multi-bit errors -- Programmable initial seed value Analog comparators (ACMP) -- Full rail to rail supply operation -- Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output -- Option to compare to fixed internal bandgap reference voltage -- Option to allow comparator output to be visible on a pin, ACMPxO Inter-integrated circuit (IIC) -- Compatible with IIC bus standard -- Multi-master operation -- Software programmable for one of 64 different serial clock frequencies -- Interrupt driven byte-by-byte data transfer -- Arbitration lost interrupt with automatic mode switching from master to slave -- Calling address identification interrupt -- Bus busy detection -- 10-bit address extension Controller area network (CAN) -- Implementation of the CAN protocol -- Version 2.0A/B - Standard and extended data frames - Zero to eight bytes data length - Programmable bit rate up to 1 Mbps - Support for remote frames -- Five receive buffers with FIFO storage scheme -- Three transmit buffers with internal prioritization using a "local priority" concept
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7
MCF51AC256 Family Configurations
*
*
*
-- Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, four 16-bit filters, or eight 8-bit filters -- Programmable wakeup functionality with integrated low-pass filter -- Programmable loopback mode supports self-test operation -- Programmable listen-only mode for monitoring of CAN bus -- Programmable bus-off recovery functionality -- Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off) -- Internal timer for time-stamping of received and transmitted messages Serial communications interfaces (SCI) -- Full-duplex, standard non-return-to-zero (NRZ) format -- Double-buffered transmitter and receiver with separate enables -- Programmable baud rates (13-bit modulo divider) -- Interrupt-driven or polled operation -- Hardware parity generation and checking -- Programmable 8-bit or 9-bit character length -- Receiver wakeup by idle-line or address-mark -- Optional 13-bit break character generation / 11-bit break character detection -- Selectable transmitter output polarity Serial peripheral interfaces (SPI) -- Master or slave mode operation -- Full-duplex or single-wire bidirectional option -- Programmable transmit bit rate -- Double-buffered transmit and receive -- Serial clock phase and polarity options -- Slave select output -- Selectable MSB-first or LSB-first shifting -- 16-bit and FIFO operations in SPI2 Input/Output -- 69 GPIOs -- 8 keyboard interrupt pins with selectable polarity -- Hysteresis and configurable pull-up device on all input pins; Configurable slew rate and drive strength on all output pins -- 16-bits Rapid GPIO pins connected to the processor's local 32-bit platform bus with set, clear, and faster toggle functionality
1.4
Part Numbers
MCF 51 AC 256 X V XX E Status (MCF = Fully Qualified ColdFire) (PCF = Product Engineering) Core Family Pb free indicator Package designator Temperature range (V = -40C to 105C, C= -40C to 85C ) CAN Feature (A: With CAN, B/C: Without CAN) Memory size designator
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 8 Preliminary--Subject to Change Without Notice Freescale Semiconductor
MCF51AC256 Family Configurations
Table 3. Orderable Part Number Summary
Freescale Part Number MCF51AC256AVFUE MCF51AC256BVFUE MCF51AC256AVLKE MCF51AC256BVLKE MCF51AC256AVPUE Description MCF51AC256 ColdFire Microcontroller with CAN MCF51AC256 ColdFire Microcontroller without CAN MCF51AC256 ColdFire Microcontroller with CAN MCF51AC256 ColdFire Microcontroller without CAN MCF51AC256 ColdFire Microcontroller with CAN Flash / SRAM (Kbytes) 256 / 32 256 / 32 256 / 32 256 / 32 256 / 32 256 / 32 128 / 32 128 / 16 128 / 32 128 / 16 128 / 32 128 / 16 Package 64 QFP 64 QFP 80 LQFP 80 LQFP 64 LQFP 64 LQFP 64 QFP 64 QFP 80 LQFP 80 LQFP 64 LQFP 64 LQFP Temperature -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C
MCF51AC256BVPUE MCF51AC256 ColdFire Microcontroller without CAN MCF51AC128AVFUE MCF51AC128 ColdFire Microcontroller with CAN
MCF51AC128CVFUE MCF51AC128 ColdFire Microcontroller without CAN MCF51AC128AVLKE MCF51AC128CVLKE MCF51AC128AVPUE MCF51AC128 ColdFire Microcontroller with CAN MCF51AC128 ColdFire Microcontroller without CAN MCF51AC128 ColdFire Microcontroller with CAN
MCF51AC128CVPUE MCF51AC128 ColdFire Microcontroller without CAN
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9
MCF51AC256 Family Configurations
1.5
Pinouts and Packaging
PTC5 / RxD2 PTC3 / TxD2 PTC2 / MCLK PTH6 / MISO2 PTH5 / MOSI2 PTH4 / SPCK2 PTC1 / SDA1 PTC0 / SCL1 VDD VSS PTG6 / EXTAL PTG5 / XTAL BKGD / MS VREFL VREFH PTD7 / KBI1P7 / AD1P15 PTD6 / FTM1CLK / AD1P14 PTD5 / AD1P13 PTD4/FTM2CLK/AD1P12 PTG4 / KBI1P4 / AD1P19 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
Figure 2 shows the pinout of the 80-pin LQFP.
PTE4 / RGPIO4 / SS1 PTE5 / RGPIO5 / MISO1 PTE6 / RGPIO6 / MOSI1 PTE7 / RGPIO7 / SPSCK1 VSS VDD PTJ4 / DDATA0 PTJ5 / DDATA1 PTJ6 / DDATA2 PTJ7 / DDATA3 PTG0 / KBI1P0 PTG1 / KBI1P1 PTG2 / KBI1P2 *PTA0 / TxCAN *PTA1 / RxCAN PTA2 PTA3 / ACMP2O PTA4 / ACMP2- PTA5 / ACMP2+ PTA6 / AD1P16
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PTC4 / SS2 IRQ / TPMCLK RESET PTF0 / RGPIO8 / FTM1CH2 PTF1 / RGPIO9 / FTM1CH3 PTF2 / RGPIO10 / FTM1CH4 PTF3 / RGPIO11 / FTM1CH5 PTF4 / RGPIO12 / FTM2CH0 PTC6 / FTM2FLT PTF7 / RGPIO15 PTF5 / RGPIO13 / FTM2CH1 PTF6 / RGPIO14 / FTM1FLT PTJ0 / PST0 PTJ1 / PST1 PTJ2 / PST2 PTJ3 / PST3 PTE0 / RGPIO0 / TxD1 PTE1 / RGPIO1 / RxD1 PTE2 / RGPIO2 / FTM1CH0 PTE3 / RGPIO3 / FTM1CH1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80-Pin LQFP
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PTG3 / KBI1P3 / AD1P18 PTD3 / KBI1P6 / AD1P11 PTD2 / KBI1P5 / AD1P10 / ACMP1O VSSAD VDDAD PTD1 / AD1P9 / ACMP1- PTD0 / AD1P8 / ACMP1+ PTB7 / AD1P7 PTB6 / AD1P6 PTB5 / AD1P5 PTB4 / AD1P4 PTB3 / AD1P3 PTB2 / AD1P2 PTB1 / TPM3CH1 / AD1P1 PTB0 / TPM3CH0 / AD1P0 PTH3 / FTM2CH5 / BKPT / AD1P23 PTH2 / FTM2CH4 / PSTCLK1 / AD1P22 PTH1 / FTM2CH3 / PSTCLK0 / AD1P21 PTH0 / FTM2CH2 / AD1P20 PTA7 / AD1P17
* TxCAN and RxCAN are not available in the members that do not support CAN
Figure 2. 80-Pin LQFP Figure 3 shows the pinout of the 64-pin LQFP and QFP.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 10 Preliminary--Subject to Change Without Notice Freescale Semiconductor
MCF51AC256 Family Configurations
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTC4 IRQ / TPMCLK RESET PTF0 / RGPIO8 / FTM1CH2 PTF1 / RGPIO9 / FTM1CH3 PTF2 / RGPIO10 / FTM1CH4 PTF3 / RGPIO11 / FTM1CH5 PTF4 / RGPIO12 / FTM2CH0 PTC6 / FTM2FLT PTF7 / RGPIO15 PTF5 / RGPIO13 / FTM2CH1 PTF6 / RGPIO14 / FTM1FLT PTE0 / RGPIO0 / TxD1 PTE1 / RGPIO1 / RxD1 PTE2 / RGPIO2 / FTM1CH0 PTE3 / RGPIO3 / FTM1CH1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PTC5 / RxD2 PTC3 / TxD2 PTC2 / MCLK PTC1 / SDA1 PTC0 / SCL1 VSS PTG6 / EXTAL PTG5 / XTAL BKGD / MS VREFL VREFH PTD7 / KBI1P7 / AD1P15 PTD6 / FTM1CLK / AD1P14 PTD5 / AD1P13 PTD4 / FTM2CLK / AD1P12 PTG4 / KBI1P4 / AD1P19
64-Pin QFP 64-Pin LQFP
PTG3 / KBI1P3 / AD1P18 PTD3 / KBI1P6 / AD1P11 PTD2 / KBI1P5 / AD1P10 /ACMP1O VSSAD VDDAD PTD1 / AD1P9 / ACMP1PTD0 / AD1P8 / ACMP1+ PTB7 / AD1P7 PTB6 / AD1P6 PTB5 / AD1P5 PTB4 / AD1P4 PTB3 / AD1P3 PTB2 / AD1P2 PTB1 / TPM3CH1 / AD1P1 PTB0 / TPM3CH0 / AD1P0 PTA7 / AD1P17
PTE4 / RGPIO4 / SS1 PTE5 / RGPIO5 / MISO1 PTE6 / RGPIO6 / MOSI1 PTE7 / RGPIO7 / SPSCK1 VSS VDD PTG0 / KBI1P0 PTG1 / KBI1P1 PTG2 / KBI1P2 *PTA0 / TxCAN *PTA1 / RxCAN PTA2 PTA3 / ACMP2O PTA4 / ACMP2PTA5 / ACMP2+ PTA6 / AD1P16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
* TxCAN and RxCAN are not available in the members that do not support CAN
Figure 3. 64-Pin QFP and LQFP Table 4 shows the package pin assignments. Table 4. Pin Availability by Package Pin-Count
Pin Number 80 1 2 3 4 5 6 7 8 64 1 2 3 4 5 6 7 8 Lowest <-Port Pin PTC4 IRQ RESET PTF0 PTF1 PTF2 PTF3 PTF4 RGPIO8 RGPIO9 RGPIO10 RGPIO11 RGPIO12 FTM1CH2 FTM1CH3 FTM1CH4 FTM1CH5 FTM2CH0 Priority --> Highest Alt 3
Alt 1 SS2 TPMCLK1
Alt 2
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11
MCF51AC256 Family Configurations
Table 4. Pin Availability by Package Pin-Count (continued)
Pin Number 80 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 64 9 10 11 12 -- -- -- -- 13 14 15 16 17 18 19 20 21 22 -- -- -- -- 23 24 25 26 27 28 29 30 31 32 33 -- -- -- -- 34 35 36 Lowest <-Port Pin PTC6 PTF7 PTF5 PTF6 PTJ0 PTJ1 PTJ2 PTJ3 PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 PTE6 PTE7 VSS VDD PTJ4 PTJ5 PTJ6 PTJ7 PTG0 PTG1 PTG2 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTA6 PTA7 PTH0 PTH1 PTH2 PTH3 PTB0 PTB1 PTB2 ACMP2O ACMP2ACMP2+ AD1P16 AD1P17 FTM2CH2 FTM2CH3 FTM2CH4 FTM2CH5 TPM3CH0 TPM3CH1 AD1P2 AD1P20 PSTCLK0 PSTCLK1 BKPT AD1P0 AD1P1 AD1P21 AD1P22 AD1P23 DDATA0 DDATA1 DDATA2 DDATA3 KBI1P0 KBI1P1 KBI1P2 TxCAN2 RxCAN3 Priority --> Highest Alt 3
Alt 1 FTM2FLT RGPIO15 RGPIO13 RGPIO14 PST0 PST1 PST2 PST3 RGPIO0 RGPIO1 RGPIO2 RGPIO3 RGPIO4 RGPIO5 RGPIO6 RGPIO7
Alt 2
FTM2CH1 FTM1FLT
TxD1 RxD1 FTM1CH0 FTM1CH1 SS1 MISO1 MOSI1 SPSCK1
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 12 Preliminary--Subject to Change Without Notice Freescale Semiconductor
MCF51AC256 Family Configurations
Table 4. Pin Availability by Package Pin-Count (continued)
Pin Number 80 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
1
Lowest <-Port Pin PTB3 PTB4 PTB5 PTB6 PTB7 PTD0 PTD1 VDDAD VSSAD PTD2 PTD3 PTG3 PTG4 PTD4 PTD5 PTD6 PTD7 VREFH VREFL BKGD PTG5 PTG6 VSS VDD PTC0 PTC1 PTH4 PTH5 PTH6 PTC2 PTC3 PTC5 MS
Priority
--> Highest Alt 3
64 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 -- 60 61 -- -- -- 62 63 64
Alt 1 AD1P3 AD1P4 AD1P5 AD1P6 AD1P7 AD1P8 AD1P9
Alt 2
ACMP1+ ACMP1-
KBI1P5 KBI1P6 KBI1P3 KBI1P4 FTM2CLK AD1P13 FTM1CLK KBI1P7
AD1P10 AD1P11 AD1P18 AD1P19 AD1P12 AD1P14 AD1P15
ACMP1O
XTAL EXTAL
SCL1 SDA1 SPCK2 MOSI2 MISO2 MCLK TxD2 RxD2
TPMCLK, FTM1CLK, and FTM2CLK options are configured via software; out of reset, FTM1CLK, FTM2CLK, and TPMCLK are available to FTM1, FTM2, and TPM3 respectively. 2 TxCAN is available in the member that supports CAN. 3 RxCAN is available in the member that supports CAN.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13
Preliminary Electrical Characteristics
2
Preliminary Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the MCF51AC256 microcontroller, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for production silicon. Finalized specifications will be published after complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this data sheet supersede any values found in the module specifications.
2.1
Parameter Classification
Table 5. Parameter Classifications
P C Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
T
D
NOTE
The classification is shown in the column labeled "C" in the parameter tables where appropriate.
2.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 6 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD).
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 14 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 6. Absolute Maximum Ratings
Rating Supply voltage Input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Maximum current into VDD Storage temperature
1
Symbol VDD VIn ID IDD Tstg
Value -0.3 to 5.8 -0.3 to VDD + 0.3 25 120 -55 to 150
Unit V V mA mA C
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption.
2.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 7. Thermal Characteristics
Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance 1,2,3,4 80-pin LQFP 1s 2s2p 64-pin LQFP 1s 2s2p 64-pin QFP 1s 2s2p
1
Symbol TA TJ
Value
Unit C C
-40 to 105 150
TBD TBD JA TBD TBD TBD TBD C/W
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15
Preliminary Electrical Characteristics
2 3
Junction to Ambient Natural Convection 1s -- Single layer board, one signal layer 4 2s2p -- Four layer board, 2 signal and 2 power layers
The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD x JA) where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD x VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273C) Solving Equation 1 and Equation 2 for K gives: K = PD x (TA + 273C) + JA x (PD)2 Eqn. 3 Eqn. 2 Eqn. 1
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
2.4
Electrostatic Discharge (ESD) Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E. A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 8. ESD and Latch-up Test Conditions
Model Human Body Series Resistance Storage Capacitance Number of Pulse per pin Machine Series Resistance Storage Capacitance Number of Pulse per pin Description Symbol R1 C -- R1 C -- Value 1500 100 3 0 200 3 pF Unit pF
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 16 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 8. ESD and Latch-up Test Conditions (continued)
Model Latch-up Description Minimum input voltage limit Maximum input voltage limit Symbol Value -2.5 7.5 Unit V V
Table 9. ESD and Latch-Up Protection Characteristics
Num 1 2 3 4 Rating Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Latch-up Current at TA = 85C Symbol VHBM VMM VCDM ILAT Min 2000 200 500 100 Max -- -- -- -- Unit V V V mA
2.5
DC Characteristics
Table 10. DC Characteristics
Num C 1 -- Operating voltage Output high voltage -- Low Drive (PTxDSn = 0) 5 V, ILoad = -4 mA 3 V, ILoad = -2 mA 5 V, ILoad = -2 mA 3 V, ILoad = -1 mA Output high voltage -- High Drive (PTxDSn = 1) 5 V, ILoad = -15 mA P 3 V, ILoad = -8 mA 5 V, ILoad = -8 mA 3 V, ILoad = -4 mA Output low voltage -- Low Drive (PTxDSn = 0) 5 V, ILoad = 4 mA 3 V, ILoad = 2 mA 5 V, ILoad = 2 mA 3 V, ILoad = 1 mA Output low voltage -- High Drive (PTxDSn = 1) 5 V, ILoad = 15 mA P 3 V, ILoad = 8 mA 5 V, ILoad = 8 mA 3 V, ILoad = 4 mA P Output high current -- Max total IOH for all ports 5V 3V Parameter Symbol Min 2.7 VDD - 1.5 VDD - 1.5 VDD - 0.8 VDD - 0.8 VDD - 1.5 VDD - 1.5 VDD - 0.8 VDD - 0.8 Typical1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IOHT -- -- -- -- Max 5.5 -- -- -- -- -- -- -- -- 1.5 1.5 0.8 0.8 1.5 1.5 0.8 0.8 100 60 Unit V
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes.
VOH
2
V
VOL
3
V
4
mA
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17
Preliminary Electrical Characteristics
Table 10. DC Characteristics (continued)
Num C 5 6 7 8 9 10 11 12 13 14 15 P Parameter Output low current -- Max total IOL for all ports 5V 3V Symbol IOLT VIH VIL Vhys
2
Min -- -- 0.65 x VDD -- 0.06 x VDD -- -- 20 20 -- 0.9 10
Typical1 -- -- -- -- 0.1 0.1 45 45 -- 1.4 --
Max 100 60 -- 0.35 x VDD 1 1 65 65 8 2.0 --
Unit mA
P Input high voltage; all digital inputs P Input low voltage; all digital inputs P Input hysteresis; all digital inputs P Input leakage current; input only pins P Internal pullup resistors
3 4
V mV A A k k pF V s
|IIn| |IOZ| RPU RPD CIn VPOR tPOR VLVD1
P High Impedance (off-state) leakage current2 P Internal pulldown resistors P POR rearm voltage D POR rearm time Low-voltage detection threshold -- high range VDD falling VDD rising Low-voltage detection threshold -- low range VDD falling VDD rising Low-voltage warning threshold -- high range 1 VDD falling VDD rising Low-voltage warning threshold -- high range 0 VDD falling VDD rising Low-voltage warning threshold low range 1 VDD falling VDD rising Low-voltage warning threshold -- low range 0 VDD falling VDD rising Low-voltage inhibit reset/recover hysteresis 5V 3V
C Input Capacitance; all non-supply pins
16
P
3.9 4.0
4.0 4.1
4.1 4.2
V
17
P
VLVD0
2.48 2.54
2.56 2.62
2.64 2.70
V
18
P
VLVW3
4.5 4.6
4.6 4.7
4.7 4.8
V
19
P
VLVW2
4.2 4.3
4.3 4.4
4.4 4.5
V
20
P
VLVW1
2.84 2.90
2.92 2.98
3.00 3.06
V
21
P
VLVW0
2.66 2.72 -- -- --
2.74 2.80 100 60 0.6
2.82 2.88 -- -- 1.0
V
22 23
T D RAM retention voltage
Vhys VRAM
mV V
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 18 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 10. DC Characteristics (continued)
Num C DC injection Parameter current5 6 7 8 (single pin limit) VIN >VDD VIN 24
D DC injection current (Total MCU limit, includes sum of all stressed pins) VIN >VDD VIN 1 2 3 4 5
6 7
8
Typical values are based on characterization data at 25C unless otherwise stated. Measured with VIn = VDD or VSS. Measured with VIn = VSS. Measured with VIn = VDD. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. The RESET pin does not have a clamp diode to VDD. Do not drive this pin above VDD.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19
Preliminary Electrical Characteristics
-6.0E-3 -5.0E-3 -4.0E-3 -3.0E-3 -2.0E-3 -1.0E-3 000E+0
Average of IOH
VDD-VOH (V)
-40C 25C 105C IOH (A) 0 0.3 0.5 0.8 VSupply-VOH 0.9 1.2 1.5 Average of IOH VDD-VOH (V) -40C 25C 105C IOH (A) 0 0.3 0.5 0.8 VSupply-VOH 0.9 1.2 1.5 MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Figure 4. Typical IOH vs. VDD-VOH at VDD = 3V (Low Drive, PTxDSn = 0)
-20.0E-3 -18.0E-3 -16.0E-3 -14.0E-3 -12.0E-3 -10.0E-3 -8.0E-3 -6.0E-3 -4.0E-3 -2.0E-3 000E+0
Figure 5. Typical IOH vs. VDD-VOH at VDD = 3V (High Drive, PTxDSn = 1)
20
Preliminary Electrical Characteristics
Average of IOH -7.0E-3 -6.0E-3 -5.0E-3
VDD-VOH (V)
-40C 25C 105C IOH (A) 0.00 0.30 0.50 0.80 VSupply-VOH 1.00 1.30 2.00 Average of IOH VDD-VOH (V) -40C 25C 105C IOH (A) 0.00 0.30 0.50 0.80 VSupply-VOH 1.00 1.30 2.00 MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
-4.0E-3 -3.0E-3 -2.0E-3 -1.0E-3 000E+0
Figure 6. Typical IOH vs. VDD-VOH at VDD = 5V (Low Drive, PTxDSn = 0)
-30.0E-3 -25.0E-3 -20.0E-3 -15.0E-3 -10.0E-3 -5.0E-3 000E+0
Figure 7. Typical IOH vs. VDD-VOH at VDD = 5 V (High Drive, PTxDSn = 1)
Freescale Semiconductor
Preliminary--Subject to Change Without Notice
21
Preliminary Electrical Characteristics
2.6
Supply Current Characteristics
Table 11. Supply Current Characteristics
Num 1 C C Parameter Run supply current3 measured at clock = 2 MHz, fBus = 1MHz) Run supply current3 measured at clock = 16 MHz, fBus = 8 MHz) Run supply current3 measured at clock = 50 MHz, fBus = 25 MHz) Stop2 mode supply current -40 C 25 C 105 C 4 C -40 C 25 C 105 C Stop3 mode supply current -40 C 25 C 105 C 5 C -40 C 25 C 105 C 6 C RTI adder to stop2 or stop34, 25C S23IDDRTI S3IDDLVD S3IDDOSC S3IDD 3 5 3 5 3 5, 3 0.90 300 300 110 90 5 TBD TBD TBD A 5 0.90 TBD TBD TBD A S2IDD 3 0.80 TBD TBD TBD A 5 0.80 TBD TBD TBD A (CPU Symbol RIDD RIDD RIDD VDD (V) 5 3 5 3 5 3 Typical1 2.67 2.64 14.8 14.7 42 41.8 Max2 TBD TBD TBD TBD TBD TBD mA mA mA Unit
2
C
(CPU
3
C
(CPU
nA nA A A A
7 8
1
C C
LVD adder to stop3 (LVDE = LVDSE = 1) Adder to stop3 for oscillator (ERCLKEN =1 and EREFSTEN = 1) enabled5
Typicals are measured at 25C. Values given here are preliminary estimates prior to completing characterization. 3 All modules clocks switch on, code run from flash, FEI mode, and does not include any dc loads on port pins. 4 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. 5 Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0).
2
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 22 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
2.7
Num 1 2 3 4 5 6 7 8
Analog Comparator (ACMP) Electricals
Table 12. Analog Comparator Electrical Specifications
C -- T D D D D D D Supply voltage Supply current (active) Analog input voltage Analog input offset voltage Analog Comparator hysteresis Analog input leakage current Analog Comparator initialization delay Bandgap Voltage Reference Factory trimmed at VDD = 3.0 V, Temp = 25C Rating Symbol VDD IDDAC VAIN VAIO VH IALKG tAINIT VBG 3.0 -- -- 1.19 Min 2.7 -- VSS - 0.3 Typical -- 20 -- 20 6.0 -- -- 1.20 Max 5.5 35 VDD 40 20.0 1.0 1.0 1.21 Unit V A V mV mV A s V
2.8
ADC Characteristics
Table 13. 5 Volt 12-bit ADC Operating Conditions
Characteristic Supply voltage Ground voltage Ref Voltage High Ref Voltage Low Input Voltage Input Capacitance Input Resistance 12 bit mode fADCK > 4MHz fADCK < 4MHz Analog Source Resistance 10 bit mode fADCK > 4MHz fADCK < 4MHz 8 bit mode (all valid fADCK) ADC Conversion Clock Freq. High Speed (ADLPC=0) Low Power (ADLPC=1) fADCK RAS -- -- -- 0.4 0.4 -- -- -- -- -- 5 10 10 8.0 MHz 4.0 Conditions Absolute Delta to VDD (VDD-VDDAD)2 Delta to VSS (VSS-VSSAD )2 Symb VDDAD VDDAD VSSAD VREFH VREFL VADIN CADIN RADIN Min 2.7 -100 -100 2.7 VSSAD VREFL -- -- Typical1 -- 0 0 VDDAD VSSAD -- 4.5 3 Max 5.5 100 100 VDDAD VSSAD VREFH 5.5 5 Unit V mV mV V V V pF k Comment
-- --
-- --
2 5 k External to MCU
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23
Preliminary Electrical Characteristics
1
Typical values assume VDDAD = 5.0 V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference.
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection
ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
+ -
+ -
CAS
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN CADIN
INPUT PIN
Figure 8. ADC Input Impedance Equivalency Diagram Table 14. 5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Characteristic Supply CurrentADLPC =1ADLSMP=1 ADCO=1 Supply CurrentADLPC =1ADLSMP=0 ADCO=1 Supply CurrentADLPC =0ADLSMP=1 ADCO=1 Supply CurrentADLPC =0ADLSMP=0 ADCO=1 Supply Current Stop, Reset, Module Off Conditions C Symb Min Typical1 Max Unit Comment
T
IDDAD
--
133
--
A
T
IDDAD
--
218
--
A
T
IDDAD
--
327
--
A
P
IDDAD
--
0.582
1
mA
IDDAD
--
0.011
1
A
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 24 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 14. 5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic ADC Asynchronous Clock Source Conversion Time (Including sample time) Sample Time Long Sample (ADLSMP=1) Total Unadjusted Error 12 bit mode 10 bit mode 8 bit mode 12 bit mode Differential Non-Linearity 10 bit mode3 8 bit mode4 12 bit mode Integral Non-Linearity 10 bit mode 8 bit mode 12 bit mode Zero-Scale Error 10 bit mode 8 bit mode 12 bit mode Full-Scale Error 10 bit mode 8 bit mode 12 bit mode Quantization Error 10 bit mode 8 bit mode 12 bit mode Input Leakage Error 10 bit mode 8 bit mode Temp Sensor Voltage Temp Sensor Slope 25C -40 C -- 25 C 25 C -- 85 C D m -- 3.638 -- D VTEMP25 D EIL D EQ T P T T P T T T T T P T T T T EFS EZS INL DNL ETUE Conditions High Speed (ADLPC=0) T Low Power (ADLPC=1) Short Sample (ADLSMP=0) T Long Sample (ADLSMP=1) Short Sample (ADLSMP=0) T tADS tADC fADACK C Symb Min 2 1.25 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typical1 3.3 2 20 40 3.5 23.5 3.0 1 0.5 1.75 0.5 0.3 1.5 0.5 0.3 1.5 0.5 0.5 1 0.5 0.5 -1 to 0 -- -- 1 0.2 0.1 1.396 3.266 Max 5 MHz 3.3 -- -- -- -- -- 2.5 1.0 -- 1.0 0.5 -- 1.0 0.5 -- 1.5 0.5 -- 1 0.5 -- 0.5 0.5 -- 2.5 1 -- -- V LSB2 Pad leakage4 * RAS LSB2 LSB2 VADIN = VDDAD LSB2 VADIN = VSSAD LSB2 LSB2 LSB2 Includes quantization ADCK cycles ADCK cycles Unit Comment tADACK = 1/fADACK
See Table 8 for conversion time variances
mV/C
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25
Preliminary Electrical Characteristics Typical values assume VDDAD = 5.0 V, Temp = 25C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH - VREFL)/2N 3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals.
1
2.9
Num C
External Oscillator (XOSC) Characteristics
Table 15. Oscillator Electrical Specifications (Temperature Range = -40 to 105C Ambient)
Rating Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) High range (RANGE = 1) FEE or FBE mode 2 High range (RANGE = 1) PEE or PBE mode 3 High range (RANGE = 1, HGO = 1) BLPE mode High range (RANGE = 1, HGO = 0) BLPE mode Symbol flo fhi-fll fhi-pll fhi-hgo fhi-lp C1 C2 Low range (32 kHz to 38.4 kHz) High range (1 MHz to 16 MHz) Series resistor Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0) High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz Crystal start-up time 4 Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0)5 High range, high gain (RANGE = 1, HGO = 1)5 Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE or FBE mode 2 PEE or PBE mode 3 BLPE mode
t t t
Min 32 1 1 1 1
Typical1 -- -- -- -- --
Max 38.4 5 16 16 8
Unit kHz MHz MHz MHz MHz
1
C
2 3
-- Load capacitors Feedback resistor --
See crystal or resonator manufacturer's recommendation. 10 1 -- -- -- -- -- -- 0 100 0 0 0 0 200 400 5 15 -- -- -- -- -- -- 0 10 20 -- -- -- -- MW
RF
4
--
RS
k
CSTL-LP
5
T
CSTL-HGO t CSTH-LP
CSTH-HGO
-- -- -- --
ms
6
T
fextal
0.03125 1 0
5 16 40
MHz
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz to 2MHz. 4 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. 5 4 MHz crystal
2
1
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 26 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
MCU EXTAL XTAL RS
RF
C1
Crystal or Resonator
C2
2.10
Num C 1 2 3 4 5 6 7
MCG Specifications
Table 16. MCG Frequency Specifications (Temperature Range = -40 to 125C Ambient)
Rating Symbol fint_ft fint_ut fint_t tirefst fdco_ut fdco_t fdco_res_t Min -- 25 31.25 -- 25.6 32 -- Typical 31.25 32.7 -- 60 33.48 -- 0.1 Max -- 41.66 39.0625 100 42.66 40 0.2 Unit kHz kHz kHz s MHz MHz %fdco
Internal reference frequency - factory P trimmed at VDD = 5 V and temperature = 25 C P P Average internal reference frequency - untrimmed 1 Average internal reference frequency - user trimmed
D Internal reference startup time DCO output frequency range untrimmed 1 -- value provided for reference: fdco_ut = 1024 X fint_ut D DCO output frequency range - trimmed Resolution of trimmed DCO output D frequency at fixed voltage and temperature (using FTRIM) Resolution of trimmed DCO output D frequency at fixed voltage and temperature (not using FTRIM) Total deviation of trimmed DCO output D frequency over voltage and temperature Total deviation of trimmed DCO output D frequency over fixed voltage and temperature range of 0 - 70 C D FLL acquisition time 2 D PLL acquisition time
3
8
fdco_res_t
--
0.2 0.5 -1.0 0.5 -- -- 0.02 -- 0.5665 --
0.4
%fdco
9
fdco_t
--
2
%fdco
10 11 12 13 14 17 18
fdco_t tfll_acquire tpll_acquire CJitter fvco fpll_jitter_625ns Dlock
-- -- -- -- 7.0 -- 1.49
1 1 1 0.2 55.0 -- 2.98
%fdco ms ms %fdco MHz %fpll %
Long term Jitter of DCO output clock D (averaged over 2ms interval) 4 D VCO operating frequency D Jitter of PLL output clock measured over 625 ns5
D Lock entry frequency tolerance 6
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27
Table 16. MCG Frequency Specifications (continued)(Temperature Range = -40 to 125C Ambient)
Num C 19 20 21 22
1 2
Rating
7
Symbol Dunl tfll_lock tpll_lock floc_low
Min 4.47 -- -- (3/5) x fint
Typical -- -- -- --
Max 5.97 tfll_acquire+ 1075(1/fint_t) tpll_acquire+
1075(1/fpll_ref)
Unit % s s kHz
D Lock exit frequency tolerance D Lock time -- FLL D Lock time -- PLL
Loss of external clock minimum D frequency - RANGE = 0
--
3
4
5
6
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0). This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the sample point of a bit using 8 time quanta per bit. Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already in lock, then the MCG may stay in lock. Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
o
7
2.11
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
Preliminary Electrical Characteristics
2.11.1
Num 1 2 3 4 5 6 7 C D D D D D D D
Control Timing
Table 17. Control Timing
Parameter Bus frequency (tcyc = 1/fBus) Internal low-power oscillator period External reset pulse width (tcyc = 1/fSelf_reset) Reset low drive Active background debug mode latch setup time Active background debug mode latch hold time IRQ pulse width Asynchronous path2 Synchronous path3 KBIPx pulse width Asynchronous path2 Synchronous path3 Port rise and fall time (load = 50 pF)4 Slew rate control disabled (PTxSE = 0), Low Drive Slew rate control enabled (PTxSE = 1), Low Drive Slew rate control disabled (PTxSE = 0), Low Drive Slew rate control enabled (PTxSE = 1), Low Drive tILIH, tIHIL 100 1.5 x tcyc 100 1.5 x tcyc -- -- ns
2
Symbol fBus tLPO textrst trstdrv tMSSU tMSH
Min dc 800 100 66 x tcyc 500 100
Typical1 --
Max 24 1500 -- -- -- --
Unit MHz s ns ns ns ns
8
D
tILIH, tIHIL
--
--
ns
9
D
tRise, tFall
-- --
11 35 40 75
ns
Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range -40 C to 105 C.
1 2
textrst RESET PIN
Figure 9. Reset Timing
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29
Preliminary Electrical Characteristics
tIHIL IRQ/KBIPx
IRQ/KBIPx tILIH
Figure 10. IRQ/KBIPx Timing
2.11.2
Timer (TPM/FTM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 18. TPM/FTM Input Timing
NUM 1 2 3 4 5 C -- -- D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTPMext tTPMext tclkh tclkl tICPW Min DC 4 1.5 1.5 1.5 Max fBus/4 -- -- -- -- Unit MHz tcyc tcyc tcyc tcyc
tTPMext tclkh
TPMxCLK tclkl
Figure 11. Timer External Clock
tICPW TPMxCHn
TPMxCHn tICPW
Figure 12. Timer Input Capture Pulse
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 30 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
2.11.3
Num 1 2
1
MSCAN
Table 19. MSCAN Wake-up Pulse Characteristics
C D D Parameter MSCAN Wake-up dominant pulse filtered MSCAN Wake-up dominant pulse pass Symbol tWUP tWUP 5 Min Typical1 Max 2 5 Unit s s
Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31
Preliminary Electrical Characteristics
2.12
SPI Characteristics
Table 20. SPI Electrical Characteristic
Num1 C Characteristic2 Operating frequency 1 D Cycle time 2 D Enable lead time 3 D Master Slave Enable lag time 4 D Master Slave Clock (SPSCK) high time Master and Slave Clock (SPSCK) low time Master and Slave Data setup time (inputs) 7 D Master Slave Data hold time (inputs) 8 9 10 11 D D D D Access time, slave3 Disable time, slave4 Master Slave Data hold time (outputs) 12
1 2
Table 20 and Figure 13 through Figure 16 describe the timing requirements for the SPI system.
Symbol
Min
Max
Unit
Master Slave Master Slave
fop fop
tSCK tSCK
fBus/2048 dc
2 4 -- 1/2
fBus/2 fBus/4
2048
Hz
-- 1/2 -- 1/2 --
-- -- -- --
tcyc
tLead tLead tLag tLag tSCKH tSCKL tSI(M) tSI(S) tHI(M) tHI(S) tA tdis tSO tSO tHO tHO
tSCK
-- 1/2 1/2 tSCK - 25 1/2 tSCK - 25 30 30
tSCK
5 6
D D
ns ns
ns
Master Slave
30 30 0 -- 25 25
-- -- 40 40 -- --
ns ns ns
Data setup time (outputs) ns
D
Master Slave
-10 -10
-- --
ns
Refer to Figure 13 through Figure 16. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Time to data active from high-impedance state. 4 Hold time to high-impedance state.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 32 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 6 MISO (INPUT) MSB IN2 11 MOSI (OUTPUT) MSB OUT2 7 BIT 6 . . . 1 11 BIT 6 . . . 1 LSB OUT LSB IN 12 2 5 4 3
5 4
NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI Master Timing (CPHA = 0)
SS(1) (OUTPUT) 2 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) 11 MOSI (OUTPUT) MSB OUT(2) 5 4 5 4 6 7 MSB IN(2) BIT 6 . . . 1 12 BIT 6 . . . 1 LSB OUT LSB IN 3
NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI Master Timing (CPHA = 1)
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33
Preliminary Electrical Characteristics
SS (INPUT) 2 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT)
NOTE:
3 5
4
5 4 11 MSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 12 SLAVE LSB OUT SEE NOTE 9
1. Not defined but normally MSB of character just received
Figure 15. SPI Slave Timing (CPHA = 0)
SS (INPUT) 2 2 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) 5 4 5 4 11 SLAVE 6 MSB IN MSB OUT 7 BIT 6 . . . 1 LSB IN 12 BIT 6 . . . 1 SLAVE LSB OUT 9 3
NOTE: 1. Not defined but normally LSB of character just received
Figure 16. SPI Slave Timing (CPHA = 1)
2.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see Chapter 4, "Memory."
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 34 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 21. Flash Characteristics
Num 1 2 3 4 5 6 7 8 9 10
1 2
C -- -- -- -- -- -- -- -- C C
Characteristic Supply voltage for program/erase Supply voltage for read operation Internal FCLK frequency2 Internal FCLK period (1/FCLK) Byte program time (random location)2 Byte program time (burst mode) Page erase time3 Mass erase time2 Program/erase endurance4 TL to TH = -40C to 105C T = 25C Data retention5
2
Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass
Min 2.7 2.7 150 5
Typical1
Max 5.5 5.5 200 6.67
Unit V V kHz s tFcyc tFcyc tFcyc tFcyc
9 4 4000 20,000 10,000 -- -- 100,000 100 -- -- --
cycles years
tD_ret
15
Typical values are based on characterization data at VDD = 5.0 V, 25C unless otherwise stated. The frequency of this clock is controlled by a software setting. 3 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
2.14
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
2.14.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35
Mechanical Outline Drawings
3
3.1
Mechanical Outline Drawings
80-pin LQFP Package
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 36 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Mechanical Outline Drawings
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37
Mechanical Outline Drawings
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 38 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Mechanical Outline Drawings
3.2
64-pin LQFP Package
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39
Mechanical Outline Drawings
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 40 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Mechanical Outline Drawings
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 41
Mechanical Outline Drawings
3.3
64-pin QFP Package
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 42 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Mechanical Outline Drawings
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 43
Mechanical Outline Drawings
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 44 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Revision History
4
Revision History
Table 22. Revision History
Revision 1 Initial published Description
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 45
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Rev.1 06/2008
Preliminary--Subject to Change Without Notice

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